Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design

Authors: Singh, K. and Rosas, O. A. R. and Jiao, H. and Huisken, J. and de Gyvez, J. P.

Abstract::Pulsed-latches emerge as an ideal sequencing element for low power digital circuit design, serving as an alternative of flip-flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the flip-flop based designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based designs.

[BibTeX] [ DOI]
@inproceedings{Singh2018a,
  author = {{Singh}, K. and {Rosas}, O. A. R. and {Jiao}, H. and {Huisken}, J. and {de Gyvez}, J. P.},
  booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
  title = {Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design},
  year = {2018},
  volume = {},
  number = {},
  pages = {1-5},
  keywords = {CMOS integrated circuits;flip-flops;logic design;low-power electronics;silicon-on-insulator;multibit pulsed-latch;flip-flop based designs;low power synchronous circuit design;low power digital circuit design;synchronous digital circuits;multibit pulsed-latches;FDSOI CMOS technology;ITC benchmark circuits;ARM Cortex-M0;Latches;Pulse generation;Clocks;Power demand;Transistors;Inverters;Libraries;Latch;flip-flop;pulse generator;time borrowing;clock distribution network;power consumption},
  doi = {10.1109/ISCAS.2018.8351251},
  issn = {2379-447X},
  url = {https://research.tue.nl/files/107219993/08351251.pdf},
  month = may
}