Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation

Authors: Singh, K. and de Bruin, B. and Huisken, J. and Jiao, H. and de Gyvez, J. P.

Abstract::Integrated systems operating in the near/sub-threshold region offer low power and energy consumption. Such systems, however, typically suffer from low efficiency in power delivery, thereby leading to ineffective power savings. In this paper, a voltage stacking system with a RISC-V microcontroller Pulpino at the bottom voltage stack and memory arrays on the top stack is proposed. The memory arrays operate at 0.7 V supply voltage, while the microcontroller operate at 0.4 V supply voltage (near/sub-threshold region) by using the leakage currents from the memory arrays. Instead of using complex voltage regulators, a simple current sink voltage controller with low area and energy overheads is used to stabilize the intermediate voltage rail between the top and bottom power domains. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 43% as compared to the conventional implementation in a flat voltage domain.

[BibTeX] [ DOI]
@inproceedings{Singh2019,
  author = {{Singh}, K. and {de Bruin}, B. and {Huisken}, J. and {Jiao}, H. and {de Gyvez}, J. P.},
  booktitle = {32nd IEEE International System-on-Chip Conference (SOCC)},
  title = {Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation},
  year = {2019},
  volume = {},
  number = {},
  pages = {370-375},
  keywords = {CMOS memory circuits;integrated circuit design;leakage currents;low-power electronics;microcontrollers;silicon-on-insulator;voltage control;voltage regulators;voltage stacked design;integrated systems;power delivery;ineffective power savings;voltage stacking system;bottom voltage stack;memory arrays;complex voltage regulators;simple current sink voltage controller;intermediate voltage rail;power domains;power consumption;flat voltage domain;near-threshold operation;sub-threshold operation;low power consumption;RISC-V microcontroller Pulpino;leakage currents;FDSOI CMOS technology;voltage 0.7 V;voltage 0.4 V;size 28 nm;Si;Power domain;charge recycling;level shifter;near/sub-threshold;current sink;voltage regulator},
  doi = {10.1109/SOCC46988.2019.1570558508},
  issn = {2164-1706},
  url = {https://research.tue.nl/en/publications/voltage-stacked-design-of-a-microcontroller-for-nearsub-threshold},
  month = sep
}