Voltage Stacking for Near / Sub-threshold Ultra-Low Power Microprocessor Systems

Authors: Singh, Kamlesh and Bruin, Barry de and Huisken, Jos and Jiao, Hailong and Corporaal, Henk

Abstract::A three-layer voltage stacking system supporting near/sub-threshold region operations is proposed in this paper. A Pulpino micro-controller and a reconfigurable accelerator are put at the bottom and middle stacks, while SRAM arrays are placed on the top stack. The micro-controller and the accelerator operate in the near/sub-threshold voltage region by only using the leakage currents from the SRAM arrays on top. Instead of using complex voltage regulators, a simple current sink voltage controller and adaptive body-bias based voltage controller with low area and energy overhead are used to stabilize the intermediate voltage rails between the top and middle as well as between the middle and bottom voltage stacks. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 30% as compared to the conventional flat implementation.

[BibTeX]
@inproceedings{Singh2019a,
  author = {Singh, Kamlesh and Bruin, Barry de and Huisken, Jos and Jiao, Hailong and Corporaal, Henk},
  booktitle = {IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S)},
  pages = {2--3},
  title = {{Voltage Stacking for Near / Sub-threshold Ultra-Low Power Microprocessor Systems}},
  year = {2019}
}