## Publications

All BrainWave publications up till now are listed below.

### 2020

1. B. de Bruin, K. Singh, J. Huisken, and H. Corporaal, “BrainWave: an energy-efficient EEG monitoring system - evaluation and trade-offs,” in IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2020.
[Abstract] [BibTeX] This paper presents the design and evaluation of an energy-efficient seizure detection system for emerging EEG-based monitoring applications, such as non-convulsive epileptic seizure detection and Freezing-of-Gait (FoG) detection. As part of the BrainWave system, a BrainWave processor for flexible and energy-efficient signal processing is designed. The key system design parameters, including algorithmic optimizations, feature offloading and near-threshold computing are evaluated in this work. The BrainWave processor is evaluated while executing a complex EEG-based epileptic seizure detection algorithm. In a 28nm FDSOI technology, 325uJ per classification at 0.9V and 290uJ at 0.5V are achieved using an optimized software-only implementation. By leveraging a Coarse-Grained Reconfigurable Array (CGRA), 160uJ and 120uJ are obtained, respectively, while maintaining a high level of flexibility. Near-threshold computing combined with CGRA acceleration leads to an energy reduction of up to 55%, including idle-time overhead.
@inproceedings{DeBruin,
author = {de Bruin, B. and Singh, K. and Huisken, J. and Corporaal, H.},
booktitle = {IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)},
isbn = {9781450370530},
keywords = {edge processing,energy-efficiency,offs,reconfigurable accelerators,system-level trade-,wearable eeg monitoring},
title = {{BrainWave: an energy-efficient EEG monitoring system - evaluation and trade-offs}},
year = {2020},
volume = {},
number = {},
pages = {xx}
}

Details
2. B. de Bruin, Z. Zivkovic, and H. Corporaal, “Quantization of deep neural networks for accumulator-constrained processors,” Microprocessors and Microsystems, 2020.
[Abstract] [BibTeX] [ Download] [ CrossRef] We introduce an Artificial Neural Network (ANN) quantization methodology for platforms without wide accumulation registers. This enables fixed-point model deployment on embedded compute platforms that are not specifically designed for large kernel computations (i.e. accumulator-constrained processors). We formulate the quantization problem as a function of accumulator size, and aim to maximize the model accuracy by maximizing bit width of input data and weights. To reduce the number of configurations to consider, only solutions that fully utilize the available accumulator bits are being tested. We demonstrate that 16 bit accumulators are able to obtain a classification accuracy within 1% of the floating-point baselines on the CIFAR-10 and ILSVRC2012 image classification benchmarks. Additionally, a near-optimal 2x speedup is obtained on an ARM processor, by exploiting 16 bit accumulators for image classification on the All-CNN-C and AlexNet networks.
@article{Bruin2020,
author = {de Bruin, Barry and Zivkovic, Zoran and Corporaal, Henk},
doi = {10.1016/j.micpro.2019.102872},
issn = {01419331},
journal = {Microprocessors and Microsystems},
keywords = {Convolutional neural networks,Efficient inference,Fixed-point,Narrow accumulators,Quantization},
pages = {102872},
publisher = {Elsevier B.V.},
title = {{Quantization of deep neural networks for accumulator-constrained processors}},
volume = {72},
url = {https://arxiv.org/pdf/2004.11783.pdf},
year = {2020}
}

Details
3. Y. Wang, X. Long, H. van Dijk, R. M. Aarts, L. Wang, and J. B. A. M. Arends, “False alarms reduction in non-convulsive status epilepticus detection via continuous EEG analysis,” Physiological Measurement, 2020.
[Abstract] [BibTeX] [ Download] [ CrossRef] Objective Frequent false alarms from computer-assisted monitoring systems may harm the safety of patients with non-convulsive status epilepticus (NCSE). In this study, we aimed at reducing false alarms in the NCSE detection based on preventing from three common errors: over-interpretation of abnormal background activity, dense short ictal discharges and continuous interictal discharges as ictal discharges. Approach We analyzed 10 participants’ hospital archived 127-hour electroencephalography (EEG) recordings with 310 ictal discharges. To reduce the false alarms caused by abnormal background activity, we used morphological features extracted by visibility graph methods in addition to time-frequency features. To reduce the false alarms caused by over-interpreting short ictal discharges and interictal discharges, we created two synthetic classes-"Suspected Non-ictal" and "Suspected Ictal"-based on the misclassified categories and constructed a synthetic 4-class dataset combining the standard two classes-"Non-ictal" and "Ictal"-to train a 4-class classifier. Precision-recall curves were used to compare our proposed 4-class classification model and the standard 2-class classification model with or without the morphological features in the leave-one-out cross validation stage. The sensitivity and precision were primarily used as performance metrics for the detection of seizure event. Main results The 4-class classification model improved the performance of the standard 2-class model, especially increased the precision by 15% at an 80% sensitivity level when only time-frequency features were used. Using the morphological features, the 4-class classification model achieved the best performances: a sensitivity of 93% ± 12% and a precision of 55% ± 30% in the group level. 100% accuracy was reached in a participant’s 4.3-hour recording with 5 ictal discharges. Significance False alarms in the NCSE detection were remarkably reduced using the morphological features and the proposed 4-class classification model.
@article{Wang2020,
author = {Wang, Ying and Long, Xi and van Dijk, Hans and Aarts, Ronald M and Wang, Lei and Arends, Johan B A M},
doi = {10.1088/1361-6579/ab8cb3},
issn = {0967-3334},
journal = {Physiological Measurement},
title = {{False alarms reduction in non-convulsive status epilepticus detection via continuous EEG analysis}},
pages = {xx},
file = {PrePrint.pdf},
year = {2020}
}

Details

### 2019

1. K. Singh, B. de Bruin, J. Huisken, H. Jiao, and J. P. de Gyvez, “Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation,” in 32nd IEEE International System-on-Chip Conference (SOCC), 2019.
[Abstract] [BibTeX] [ Download] [ CrossRef] Integrated systems operating in the near/sub-threshold region offer low power and energy consumption. Such systems, however, typically suffer from low efficiency in power delivery, thereby leading to ineffective power savings. In this paper, a voltage stacking system with a RISC-V microcontroller Pulpino at the bottom voltage stack and memory arrays on the top stack is proposed. The memory arrays operate at 0.7 V supply voltage, while the microcontroller operate at 0.4 V supply voltage (near/sub-threshold region) by using the leakage currents from the memory arrays. Instead of using complex voltage regulators, a simple current sink voltage controller with low area and energy overheads is used to stabilize the intermediate voltage rail between the top and bottom power domains. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 43% as compared to the conventional implementation in a flat voltage domain.
@inproceedings{Singh2019,
author = {{Singh}, K. and {de Bruin}, B. and {Huisken}, J. and {Jiao}, H. and {de Gyvez}, J. P.},
booktitle = {32nd IEEE International System-on-Chip Conference (SOCC)},
title = {Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation},
year = {2019},
volume = {},
number = {},
pages = {370-375},
keywords = {CMOS memory circuits;integrated circuit design;leakage currents;low-power electronics;microcontrollers;silicon-on-insulator;voltage control;voltage regulators;voltage stacked design;integrated systems;power delivery;ineffective power savings;voltage stacking system;bottom voltage stack;memory arrays;complex voltage regulators;simple current sink voltage controller;intermediate voltage rail;power domains;power consumption;flat voltage domain;near-threshold operation;sub-threshold operation;low power consumption;RISC-V microcontroller Pulpino;leakage currents;FDSOI CMOS technology;voltage 0.7 V;voltage 0.4 V;size 28 nm;Si;Power domain;charge recycling;level shifter;near/sub-threshold;current sink;voltage regulator},
doi = {10.1109/SOCC46988.2019.1570558508},
issn = {2164-1706},
url = {https://research.tue.nl/en/publications/voltage-stacked-design-of-a-microcontroller-for-nearsub-threshold},
month = sep
}

Details
2. Y. Wang, M. X. Cohen, J. Nonnekes, and R. V. Wezel, “EEG analysis of Freezing of Gait in local-moving experiment,” in Abstract for 7th Dutch Bio-Medical Engineering Conference (BME2019), 2019.
[Abstract] [BibTeX] [ Download] Freezing of gait (FOG) is a motor symptom, which is described as feet that seem to be glued on the floor by patients with Parkinson’s disease (PD). Several cueing‐strategies, e.g. rhythmic auditory or visual cues, may help PD patients overcome FOG. The on-demand manner cueing (i.e. cueing only occurring when FOG is detected, and preferably predicted) would further improve the feasibility in daily life. Current studies mainly analyze movement patterns (via 3D gyroscopes or accelerometers) to detect FOG. However, these studies are limited by their ability to at best detect, but not predict FOG. The possibility of using electroencephalography (EEG) to predict FOG (detect the transition between normal walking and FOG) was proposed by Handojoseno [1]. In his study, 4-channel EEG data was acquired and analyzed, which is not yet sufficiently accurate for FOG prediction and detection. Our study therefore focuses on real‐time detection and prediction of FOG, with not only EEG, but also Electrocardiogram (ECG) and motion sensor data. Ultimately, we aim to develop a ‘brainwave’ chip, which can monitor the EEG signals of PD patients. An automatic FOG detection/prediction algorithm applied on this chip is under investigation. This is an explorative observational study. Fifteen patients with idiopathic Parkinson’s disease (Hoehn and Yahr scale [2, 4]) at off-medication state were asked to execute three tasks in place (two minutes per task) at each session: stepping, normal half turning, and rapid half turning. The following data were acquired during the sessions: 64-channel EEG data (ActiCap), motion data from 6 accelerometers (TMSi; applied above ankles, knees, and metacarpophalangeal joints) and 8 footswitches (TMSi; 4 per foot), EMG data (TMSi; 1 sensor per forearm), and 3-lead ECG data. The experiment was videotaped, and two independent raters annotated the presence of FOG via the videos. Our results show that rapid half turning especially evokes FOG in Parkinson patients. The EEG signals correlated with the FOG episodes were time-frequency analyzed. Based on our preliminary results, we hypothesize that EEG signals present different patterns during FOG in each condition (task), and each subject bring differences in the patterns.
@inproceedings{Wang2019a,
author = {Wang, Ying and Cohen, Mike X and Nonnekes, Jorik and Wezel, Richard Van},
booktitle = {Abstract for 7th Dutch Bio-Medical Engineering Conference (BME2019)},
file = {BME2019FOG_Wang_Ying.pdf},
title = {{EEG analysis of Freezing of Gait in local-moving experiment}},
pages = {xx},
year = {2019}
}

Details
3. K. Singh, B. de Bruin, J. Huisken, H. Jiao, and H. Corporaal, “Voltage Stacking for Near / Sub-threshold Ultra-Low Power Microprocessor Systems,” in IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
[Abstract] [BibTeX] A three-layer voltage stacking system supporting near/sub-threshold region operations is proposed in this paper. A Pulpino micro-controller and a reconfigurable accelerator are put at the bottom and middle stacks, while SRAM arrays are placed on the top stack. The micro-controller and the accelerator operate in the near/sub-threshold voltage region by only using the leakage currents from the SRAM arrays on top. Instead of using complex voltage regulators, a simple current sink voltage controller and adaptive body-bias based voltage controller with low area and energy overhead are used to stabilize the intermediate voltage rails between the top and middle as well as between the middle and bottom voltage stacks. To the best of our knowledge, this is the first work proposing voltage stacking for near/sub-threshold systems. Implemented in a 28-nm FDSOI CMOS technology, the proposed voltage stacking system reduces the power consumption by up to 30% as compared to the conventional flat implementation.
@inproceedings{Singh2019a,
author = {Singh, Kamlesh and Bruin, Barry de and Huisken, Jos and Jiao, Hailong and Corporaal, Henk},
booktitle = {IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S)},
pages = {2--3},
title = {{Voltage Stacking for Near / Sub-threshold Ultra-Low Power Microprocessor Systems}},
year = {2019}
}

Details
4. Y. Wang, X. Long, J. P. van Dijk, R. H. C. Lazeron, R. M. Aarts, and J. B. A. M. Arends, “Non-convulsive status epilepticus detection,” in Abstract for 7th Dutch Bio-Medical Engineering Conference (BME2019), 2019.
[Abstract] [BibTeX] [ Download] Non-convulsive status epilepticus (NCSE) is an epileptic process, where electrographic seizure activity persists over 10 minutes without noticeable motor symptoms [1]. Long-term NCSE with high degree of unresponsiveness may result in structural brain damage for the ICU patients. During the patients’ hospital stay, it is practically difficult to constantly make precise diagnosis of NCSE by clinicians via a routine procedure. Given the subtle and variable clinical symptoms, clinicians widely use electroencephalography (EEG) to diagnose NCSE. The ictal discharges during NCSE are visually analyzed by the clinicians based on some common morphological EEG patterns. However, the visual inspection by humans is time-consuming and subjective. Moreover, the safety of the chronic patients with NCSE is not guaranteed without proper monitoring. Daily monitoring of these patients unduly burdens their caregivers. Therefore, a 24/7 automatic NCSE detection system via continuous EEG signals is desirable at both hospital and home. We aim to develop a ‘brainwave’ chip, which can constantly monitor the EEG signals from NCSE patients. An automatic NCSE detection algorithm applied on this chip is investigated. This is a retrospective observational study with existing EEG and one-lead ECG recordings from two groups: 16 participants with a clinical diagnosis of NCSE and a control group of 12 participants where a clinically suspected NCSE was not confirmed. The NCSE detection system was built and validated on the training and testing dataset in the NCSE group, respectively. Around 15 features were mainly extracted from the time and frequency domains of EEG signals [2]. We trained a 3-class RUSBoost classifier to score each epoch (2.56 seconds) in three categories: ictal, abnormal activities, and normal activities. The abnormal activities mainly indicate the electrographic activity during the transition between ictal and normal activities. The decision of the ictal or normal-activity event was based on the evolution of three-category scores in 20-second window. As a preliminary result, a 5-fold cross validation method was executed to achieve the classification performance within one subject. About 85% of ictal events could be detected using our system, and its precision achieves 78%. The performance of each participant will be presented in future work. Non-convulsive status epilepticus (NCSE) is an epileptic process, where electrographic seizure activity persists over 10 minutes without noticeable motor symptoms [1]. Long-term NCSE with high degree of unresponsiveness may result in structural brain damage for the ICU patients. During the patients’ hospital stay, it is practically difficult to constantly make precise diagnosis of NCSE by clinicians via a routine procedure. Given the subtle and variable clinical symptoms, clinicians widely use electroencephalography (EEG) to diagnose NCSE. The ictal discharges during NCSE are visually analyzed by the clinicians based on some common morphological EEG patterns. However, the visual inspection by humans is time-consuming and subjective. Moreover, the safety of the chronic patients with NCSE is not guaranteed without proper monitoring. Daily monitoring of these patients unduly burdens their caregivers. Therefore, a 24/7 automatic NCSE detection system via continuous EEG signals is desirable at both hospital and home. We aim to develop a ‘brainwave’ chip, which can constantly monitor the EEG signals from NCSE patients. An automatic NCSE detection algorithm applied on this chip is investigated. This is a retrospective observational study with existing EEG and one-lead ECG recordings from two groups: 16 participants with a clinical diagnosis of NCSE and a control group of 12 participants where a clinically suspected NCSE was not confirmed. The NCSE detection system was built and validated on the training and testing dataset in the NCSE group, respectively. Around 15 features were mainly extracted from the time and frequency domains of EEG signals [2]. We trained a 3-class RUSBoost classifier to score each epoch (2.56 seconds) in three categories: ictal, abnormal activities, and normal activities. The abnormal activities mainly indicate the electrographic activity during the transition between ictal and normal activities. The decision of the ictal or normal-activity event was based on the evolution of three-category scores in 20-second window. As a preliminary result, a 5-fold cross validation method was executed to achieve the classification performance within one subject. About 85% of ictal events could be detected using our system, and its precision achieves 78%. The performance of each participant will be presented in future work.
@conference{cbe202944d544ab48d3067b473be1264,
annote = {7th Dutch Bio-Medical Engineering Conference (BME2019) ; Conference date: 24-01-2019 Through 25-01-2019},
author = {Wang, Y and Long, X and van Dijk, J P and Lazeron, R H C and Aarts, R M and Arends, J.B.A.M.},
booktitle = {Abstract for 7th Dutch Bio-Medical Engineering Conference (BME2019)},
file = {BME2019NCSE_YingWang.pdf},
title = {{Non-convulsive status epilepticus detection}},
pages = {xx},
year = {2019}
}

Details
5. W.-T. Wong, K. Singh, J. Huisken, and J. Pineda de Gyvez, “Power and Variation Improved Near-Vt Standard Cell Library for 28-nm FDSOI,” in IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
[Abstract] [BibTeX] In this work, a new library is developed for 28- nm FDSOI CMOS technology. The new library is optimized for near-threshold operating voltage of 0.4 V by balancing the pullup/pull-down networks (PUN/PDN) of logic gates, focusing on device sizing and exploiting poly-biasing feature. With the new library, up to 38% of leakage power consumption savings and up to 9% of dynamic power consumption savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the existing library. Combining the newly developed library with the existing libraries reduces the power consumption even more without any performance and area penalty. Monte Carlo simulations on the critical path delay of the ARM CortexM0 shows that the mean and standard deviation decreased by up to 8% and 22%, respectively, improving speed and robustness.
@inproceedings{Wong2019,
author = {Wong, Wing-Tsi and Singh, Kamlesh and Huisken, Jos and {Pineda de Gyvez}, Josė},
booktitle = {IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S)},
pages = {20.01},
title = {{Power and Variation Improved Near-Vt Standard Cell Library for 28-nm FDSOI}},
year = {2019}
}

Details
6. H. Du, Y. Wang, X. Long, J. B. A. M. Arends, J. P. van Dijk, and R. M. Aarts, “Visibility graph methods in nonconvulsive seizure detection,” in Abstract for 7th Dutch Bio-Medical Engineering Conference (BME2019), 2019.
[Abstract] [BibTeX] [ Download] With the development of the visibility graph, a single-channel EEG signal can be characterized in the graph domain as well.
@inproceedings{Du2019,
title = {Visibility graph methods in nonconvulsive seizure detection},
author = {Du, Hui and Wang, Y. and Long, X. and Arends, J.B.A.M. and {van Dijk}, J.P. and Aarts, R.M.},
year = {2019},
language = {English},
pages = {xx},
booktitle = {Abstract for 7th Dutch Bio-Medical Engineering Conference (BME2019)},
file = {long19_c01_preprint_DBME.pdf}
}

Details

### 2018

1. Y. Wang, X. Long, H. v. Dijk, R. Aarts, and J. Arends, “Adaptive EEG Channel Selection for Nonconvulsive Seizure Analysis,” in IEEE 23rd International Conference on Digital Signal Processing (DSP), 2018.
[Abstract] [BibTeX] [ Download] [ CrossRef] A preliminary work of the nonconvulsive seizure detection system is presented here. The system aims at detecting nonconvulsive seizures for epilepsy patients, targeting a 24/7 monitoring based on continuous electroencephalography (EEG) signals. It has been observed that the interesting seizure-related brain activities in some of the multi-channel EEG signals were weak, often with a noisy background or artifacts, and this might also be patient-dependent. Therefore, using the “best” channels with a good signal quality is expected to enhance the seizure detection performance. This paper describes a method to select the “best” EEG channels adaptively from the data of nonconvulsive seizure patients. A signal quality index (SQI) was proposed, where a higher SQI of a channel (signal) indicates a stronger brain activity associated with the ictals of nonconvulsive seizures and less artifacts. The validity of the SQI for adaptive channel selection is demonstrated in this paper. Advantages and limitations of our proposed method were discussed.
@inproceedings{Wang2019,
author = {{Wang}, Y. and {Long}, X. and v. {Dijk}, H. and {Aarts}, R. and {Arends}, J.},
booktitle = {IEEE 23rd International Conference on Digital Signal Processing (DSP)},
title = {Adaptive EEG Channel Selection for Nonconvulsive Seizure Analysis},
year = {2018},
volume = {},
number = {},
pages = {1-5},
keywords = {bioelectric potentials;electroencephalography;medical disorders;medical signal processing;neurophysiology;patient monitoring;signal classification;epilepsy patients;continuous electroencephalography signals;multichannel EEG signals;seizure detection performance;nonconvulsive seizure patients;signal quality index;adaptive channel selection;adaptive EEG channel selection;nonconvulsive seizure detection system;seizure-related brain activity;Electroencephalography;Time-frequency analysis;Brain;Discharges (electric);Electrodes;Noise measurement;Feature extraction;nonconvulsive seizure;EEG;Channel selection},
doi = {10.1109/ICDSP.2018.8631844},
issn = {2165-3577},
url = {https://research.tue.nl/files/121932638/08631844.pdf},
month = nov
}

Details
2. B. de Bruin, Z. Zivkovic, and H. Corporaal, “Quantization of Constrained Processor Data Paths Applied to Convolutional Neural Networks,” in 21st Euromicro Conference on Digital System Design (DSD), 2018.
[Abstract] [BibTeX] [ Download] [ CrossRef] Artificial Neural Networks (NNs) can effectively be used to solve many classification and regression problems, and deliver state-of-the-art performance in the application domains of natural language processing (NLP) and computer vision (CV). However, the tremendous amount of data movement and excessive convolutional workload of these networks hampers large-scale mobile and embedded productization. Therefore these models are generally mapped to energy-efficient accelerators without floating-point support. Weight and data quantization is an effective way to deploy high-precision models to efficient integer-based platforms. In this paper a quantization method for platforms without wide accumulation registers is being proposed. Two constraints to maximize the bit width of weights and input data for a given accumulator size are introduced. These constraints exploit knowledge about the weight and data distribution of individual layers. Using these constraints, we propose a layer-wise quantization heuristic to find a good fixed-point network approximation. To reduce the number of configurations to consider, only solutions that fully utilize the available accumulator bits are being tested. We demonstrate that 16-bit accumulators are able to obtain a Top-1 classification accuracy within 1% of the floating-point baselines on the CIFAR-10 and ILSVRC2012 image classification benchmarks.
@inproceedings{8491840,
author = {{de Bruin}, B. and {Zivkovic}, Z. and {Corporaal}, H.},
booktitle = {21st Euromicro Conference on Digital System Design (DSD)},
title = {Quantization of Constrained Processor Data Paths Applied to Convolutional Neural Networks},
year = {2018},
volume = {},
number = {},
pages = {357-364},
keywords = {computer vision;convolution;feedforward neural nets;fixed point arithmetic;image classification;natural language processing;NNs;regression problems;NLP;computer vision;data movement;embedded productization;energy-efficient accelerators;floating-point support;data quantization;integer-based platforms;accumulation registers;accumulator bits;convolutional workload;processor data paths;image classification;precision models;artificial neural networks;convolutional neural networks;floating-point baselines;fixed-point network approximation;layer-wise quantization;data distribution;Quantization (signal);Computational modeling;Benchmark testing;Kernel;Mathematical model;Convolutional neural networks;quantization, fixed-point efficient inference, narrow accumulators, convolutional neural networks},
doi = {10.1109/DSD.2018.00069},
issn = {},
url = {https://research.tue.nl/files/112931714/08491840.pdf},
month = aug
}

Details
3. K. Singh, O. A. R. Rosas, H. Jiao, J. Huisken, and J. P. de Gyvez, “Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design,” in IEEE International Symposium on Circuits and Systems (ISCAS), 2018.
[Abstract] [BibTeX] [ Download] [ CrossRef] Pulsed-latches emerge as an ideal sequencing element for low power digital circuit design, serving as an alternative of flip-flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the flip-flop based designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based designs.
@inproceedings{Singh2018a,
author = {{Singh}, K. and {Rosas}, O. A. R. and {Jiao}, H. and {Huisken}, J. and {de Gyvez}, J. P.},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
title = {Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design},
year = {2018},
volume = {},
number = {},
pages = {1-5},
keywords = {CMOS integrated circuits;flip-flops;logic design;low-power electronics;silicon-on-insulator;multibit pulsed-latch;flip-flop based designs;low power synchronous circuit design;low power digital circuit design;synchronous digital circuits;multibit pulsed-latches;FDSOI CMOS technology;ITC benchmark circuits;ARM Cortex-M0;Latches;Pulse generation;Clocks;Power demand;Transistors;Inverters;Libraries;Latch;flip-flop;pulse generator;time borrowing;clock distribution network;power consumption},
doi = {10.1109/ISCAS.2018.8351251},
issn = {2379-447X},
url = {https://research.tue.nl/files/107219993/08351251.pdf},
month = may
}

Details
4. K. Singh, H. Jiao, J. Huisken, H. Fatemi, and J. P. de Gyvez, “Low power latch based design with smart retiming,” in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
[Abstract] [BibTeX] [ Download] [ CrossRef] Flip-flops and latches are two options to construct pipelines in digital integrated circuits (ICs). In this paper, the implications for converting a flip-flop based design to a latch-based design are investigated by performing timing and power analysis. Design flows are also proposed to convert a flip-flop based design to a latch-based design as well as a latch/flip-flop-mixed design. With a new retiming strategy, the optimum operating condition is identified for both the latch based design and the mixed design, where the maximum time borrowing or performance enhancement can be obtained. Compared to the flip-flop based design, 48% and 45% frequency boosting are achieved by the latch based design and the mixed design, respectively. While maintaining the same performance as the flip-flop based design with the aid of supply voltage scaling, the latch based design and the mixed design reduce the power consumption by 21% and 16%, respectively, in an industrial 28-nm FDSOI CMOS technology.
@inproceedings{Singh2018,
author = {{Singh}, K. and {Jiao}, H. and {Huisken}, J. and {Fatemi}, H. and {de Gyvez}, J. P.},
booktitle = {19th International Symposium on Quality Electronic Design (ISQED)},
title = {Low power latch based design with smart retiming},
year = {2018},
volume = {},
number = {},
pages = {329-334},
keywords = {CMOS integrated circuits;digital integrated circuits;flip-flops;logic design;low-power electronics;silicon-on-insulator;flip-flop based design;low power latch based design;smart retiming;digital integrated circuits;timing power analysis;latch-flip-flop-mixed design;FDSOI CMOS technology;power consumption;size 28 nm;Si;Latches;Power demand;Clocks;Timing;Pipelines;Integrated circuits;Flip-flops;Latch;flip-flop;voltage scaling;time borrowing;power consumption},
doi = {10.1109/ISQED.2018.8357308},
issn = {},
url = {https://research.tue.nl/files/99956387/singhlow2018.pdf},
month = mar
}

Details
5. K. Van Dijsseldonk, Y. Wang, R. Van Wezel, B. R. Bloem, and J. Nonnekes, “Provoking freezing of gait in clinical practice: turning in place is more effective than stepping in place,” Journal of Parkinson’s Disease, 2018.
@article{VanDIjsseldonk2018a,
title = {Provoking freezing of gait in clinical practice: turning in place is more effective than stepping in place},
keywords = {clinical assessment, Freezing of gait, gait, Parkinson's disease, Humans, Middle Aged, Male, Neurologic Examination, Gait/physiology, Aged, 80 and over, Female, Aged, Parkinson Disease/diagnosis},
author = {{Van Dijsseldonk}, Karlijn and Wang, Ying and {Van Wezel}, Richard and Bloem, {Bastiaan R.} and Nonnekes, Jorik},
year = {2018},
month = jan,
day = {1},
doi = {10.3233/JPD-181332},
language = {English},
volume = {8},
pages = {363--365},
journal = {Journal of Parkinson's Disease},
issn = {1877-7171},
publisher = {IOS Press},
url = {https://research.tue.nl/files/101019380/jpd_2F2018_2F8_2_2Fjpd_8_2_jpd181332_2Fjpd_8_jpd181332.pdf},
number = {2}
}

Details

### 2017

1. M. V. Leussen, J. Huisken, L. Wang, H. Jiao, and J. P. de Gyvez, “Reconfigurable Support Vector Machine Classifier with Approximate Computing,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017.
[Abstract] [BibTeX] [ Download] [ CrossRef] Support Vector Machine (SVM) is one of the most popular machine learning algorithms. An energy-efficient SVM classifier is proposed in this paper, where approximate computing is utilized to reduce energy consumption and silicon area. A hardware architecture with reconfigurable kernels and overflow-resilient limiter is presented. For different applications, different kernels can be chosen and configured to achieve the optimum energy efficiency while achieving the performance requirement. For an epileptic seizure detection application, on average, 15% energy and 14% area savings are achieved with the proposed approximate SVM classifier compared to a fully-accurate SVM implementation with almost no accuracy degradation.
@inproceedings{Leussen2017SVM,
author = {Leussen, Martin Van and Huisken, Jos and Wang, Lei and Jiao, Hailong and de Gyvez, Jos{\'e} Pineda},
booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
title = {Reconfigurable Support Vector Machine Classifier with Approximate Computing},
year = {2017},
volume = {3},
number = {},
pages = {13-18},
keywords = {energy conservation;pattern classification;support vector machines;SVM;approximate computing;energy consumption reduction;energy-efficient SVM classifier;hardware architecture;machine learning algorithms;overflow-resilient limiter;reconfigurable kernels;reconfigurable support vector machine classifier;silicon area reduction;Approximate computing;Computer architecture;Hardware;Kernel;Support vector machine classification;Training;Machine learning;approximate multiplier;energy efficiency;reconfigurable architecture},
doi = {10.1109/ISVLSI.2017.13},
issn = {},
month = jul,
url = {https://research.tue.nl/files/78140508/07987488.pdf},
organization = {IEEE}
}

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