Kees Goossens, Full Professor
PositionFull-time full professor in Real-Time Embedded Systems
in the Electronic Systems group
in the Electrical Engineering faculty
at the Eindhoven University of Technology (TU/e).
The Eindhoven University of Technology is ranked high in university rankings.
- Hadi Ahmadi successfully defended his thesis. See the publication page for his thesis.
- Reinier van Kampenhout successfully defended his thesis. See the publication page for his thesis.
- Zhan's paper "Defect Location Identification for Cell-Aware Test" received the best paper award in the LATS'19 conference! This is a video of the same paper.
Fully functional silicon of a three-core CompSOC platform with network on chip!
Photo of CompSOC by K.G.W. Goossens et al.
- Rasool Tavakoli successfully defended his thesis. See the publication page for his thesis.
- Gabriela Breaban successfully defended her thesis. See the publication page for her thesis.
- Yonghui Li successfully defended his thesis. See the publication page for his thesis.
- Manil Dev Gomony and Sven Goossens successfully defended their theses. See the publication page for their theses.
- Karthik Chandrasekar, Pavel Zaykov, Ashkan Beyranvand Nejad, and Andrew Nelson all successfully defended their theses. See the publication page for their theses.
- We released our RTMemController, an open-source WCET and ACET analysis tool for real-time memory, as published in our ECRTS'14 paper.
- We received the HiPEAC award for our 2013 DAC paper "Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach".
We released a new Version 3.1 of DRAMPower, the Open Source
DRAM Power and Energy Estimation Tool.
The DRAMPower tool performs DRAM command trace analysis based on memory state transitions and hence, avoids cycle-by-cycle evaluation, thus speeding up simulations. The tool supports all basic DRAM memory operations including read, write, refresh, activate, precharge and auto-precharge, besides active and precharged power-down and self-refresh modes. The tool has also been extended to support power estimation of dual-rank DIMMs including IO and Termination power. This feature also enables power estimation of multiple 3D-stacked Wide IO DRAM dies (equivalent to multiple ranks). Finally, the tool also supports variation-aware power estimation, for a selection of DDR3 memories manufactured at 50nm process technology, based on the Monte-Carlo analysis presented in our DAC'13 article. Check it out now at www.drampower.info.
- composability (cf. virtualisation, partitioning), especially of temporal behaviour
- predictability, for real-time applications
- abstraction, especially transaction-based communication-centric debug
- real-time microkernels, real-time operating systems
- models of computation and models of execution
- especially the Aethereal Network on Chip (NOC) developed since 2001 by Philips/NXP Research
- network on chip design flows
- hardwired networks on chip in FPGAs
- network on chip as test access mechanism (TAM)
- uses of networks on chip, e.g. for internet router crossbars
- communication protocols
Finished projects are: 3DIM3, BENEFIC, Cobra, COMCAS, DEWI, EMC2, Flextiles, INDEXYS, MESA, NEST, NEVA, OpenES, RESIST, SCALOPES, T-CREST, TSAR.
All the research is in collaboration with MSc and PhD students, postdocs, Electronics Systems staff, and other researchers at NXP Semiconductors, Delft university of technology, and other (Dutch) universities.
- TODAES 2009-present Editorial board member for the Association for Computing Machinery (ACM) Transactions on Design Automation of Electronic Systems.
- DAEM 2006-present Associate editor for the Springer Journal of Design Automation of Embedded Systems.
- IJECRTS 20011-2013 Editorial Review Board member of the Resources Management Association (IRMA) International Journal of Embedded and Real-Time Communication Systems.
- CDT 2008 Guest editor for the IET Computers and Digital Techniques special issue on networks on chip.
- DAEM 2011 Guest editor for the Springer Journal of Design Automation of Embedded Systems for the special issue on on Networks on chips: design flows and case studies.
- System Architect at Topic Embedded Products in Best (2016-2019).
- Senior Principal Research Scientist at NXP Semiconductors (formerly Philips) Research (September 1995 to December 2009).
- Part-time Adjunct (Full) Professor (Buitengewoon Hoogleraar) at Computer Engineering group at the Delft University of Technology (February 2007 to December 2009).
- Post-doctoral positions at the Departamento de Informatica, Universidade Federal de Pernambuco, Brazil, and Dipartimento di Scienze dell'Informazione, Universita di Roma "La Sapienza", Italy (1993-1995).
- My PhD in Computer Science is from the Laboratory for Foundations of Computer Science, of the University of Edinburgh, UK (1998-1993). My thesis treated Embedding Hardware Description Languages in Proof Systems, which involved operational semantics for a subset of the ELLA hardware description language, and embedded this semantics in the higher-order-logic proof system Lambda, and proving various properties about the embedded semantics, formal hardware synthesis, and symbolic simulation.
- My BSc in Computer Science and Pure Mathematics is from the Computer Science department of the University of Wales, UK (1984-1988).
Previous Research Topics
- automated theorem proving for hardware verification. In particular, my PhD thesis describes the embedding of the formal semantics of a hardware description language (ELLA, VHDL, etc.) in the Lambda higher-order logic theorem prover.
- high-level hardware synthesis design flow for high-throughput video processing, in particular the Philips Phideo architecture and design flow.
- on-chip communication protocols for global (interchannel) resource management, and dynamic reconfiguration.