Teaching

I am currently a teaching assistant for the following courses:

Previously supervised courses:

  • 5DD17 Circuit Analysis
  • 5HH00 Electronics for embedded systems
  • 5VT11 Skills training: FPGA and Verilog

Workshops

In parallel to my teaching activities I also hold workshops for industrial parties on topics related to the design and use of modern compilers. More information on this can be found here.

Bachelor and Master final projects

Compiler and toolchain support for the CLP processor

spacebel

A new control-loop processor has been designed by SABCA (a Belgian earospace company) which has been selected by ESA to power the thrust-vector control of the Vega thruster and the Ariane 6 booster's thrusters. This processor is currently programmed by hand in assembly but a toolflow starting at higher abstraction levels (up to Matlab/simulink) is under development. In cooperation with Spacebel we are currently working on a LLVM backend for this processor architecture. Do you think you have what it takes to help us?

Compiler backends for our own hardware platforms

SIMD architecture

There are currently two hardware architectures (CGRA and SIMD) being researched within the ES group, both of them need good compiler support in order to be usable by anyone but an expert. However, some of the advanced architectural features within these architectures don't fit really well within the existing LLVM compiler framework (or most other frameworks that we are familiar with).

Both these architectures provide support for register file bypassing. A technique for avoiding unnessecary reads and writes in the register file which can result in significant energy improvements. In the case of these architectures the bypassing this explicitly stated in the program and completely controlled by the compiler. However, this is not something that the current LLVM framework is designed for but several techniques for implementing this are considered. It's up to you to find a good (and generic) way to put this into the framework so that both architectures can benefit from it.

Compiler support for real-time system development

Using heterogeneous systems for real-time system development requires good estimates of the worst case execution time bounds for application (parts) running on each of the processors in the system. Several tools already exist to anaylze applications after the compilation has completed but each of these tools is usually aimed at one (or a few) of the architecture types within the system. Furthermore, these tools need to extract information from the executable which is usually available within the compiler. In this assignment you will look into integrating the worst-case execution time analysis in the compiler backend such that the compiler can directly generate a worst-case execution time analysis report together with the compiled application. Thus enabling the use of the more detailed information that we lost when exiting the compiler and by using a separate analysis utility.

Programability of heterogeneous systems

Heterogeneous computing is becoming more prevalent as a solution for high-performance energy-efficient computing. However, programming computer systems composed of different kinds of processing is proving to be difficult.

Several new programming models targeting these heterogeneous systems have emerged in the recent years but a good overview of the capabilities and efficiency (both in writing the code and the resulting performance) is still missing.

Examples of such high-level programming models can be:

Comparing the features and performance of these languages could be done as a masters project or as a set of several bachelor projects.