HiPEAC Logo Tutorial: Designing Next-Generation Real-Time Streaming Systems

Novel embedded systems, such as smart phones, have to execute multiple streaming applications concurrently. A user may, for example, use a mobile phone to watch a video that is being decoded using an MPEG-4 decoder while an MP3 decoder is used to decode the accompanying audio. The applications may use an Internet connection that requires a software-defined radio protocol to download the required bit streams. The user expects that these applications have a robust behavior and that their performance is guaranteed. At the same time, the resource usage of these applications should be kept as small as possible in order to reduce cost both in terms of area and energy.

In the architecture domain there is a clear trend to use heterogeneous multi-processor systems-on-chip (MPSoCs) to meet the requirements of next-generation real-time streaming systems at an affordable area and energy cost. Designing these systems is a very challenging task, especially since the interactions between all hardware and software components need to be considered to provide timing guarantees. Predictable MPSoC platforms in combination with a model-based design approach based on the dataflow model-of-computation have emerged as a promising solution to address this design challenge. This tutorial presents a complete overview of the dataflow model-of-computation, a predictable MPSoC platform, and the model-based design approaches needed to design next-generation embedded systems for real-time streaming applications. The tutorial includes a hands-on session in which the participants apply this theory to a practical example.


Overview of the tutorial

The tutorial focuses on the challenges involved in the design of systems that provide timing guarantees to streaming applications. It first discusses how modern streaming applications can be modeled using the dataflow model-of-computation. A state-of-the-art software-defined radio application from industry is used to illustrate this modeling process. Next, the tutorial shifts attention to the MPSoC platform. The speakers explain the design alternatives to consider in the development of a hardware platform that is to provide timing guarantees to streaming applications. The predictable and composable MPSoC (CoMPSoC) platform from TU Eindhoven and the precision-timed (PRET) architecture from UC Berkeley are used to show the audience practical example platforms that provide these timing guarantees. To successfully build a system, applications need to be mapped to these platforms under given timing constraints. The speakers first give an overview of existing timing-analysis techniques for dataflow graphs. These techniques can be applied to applications modeled with a dataflow graph. The speakers further explain how hardware archictures and mapping decisions can be modeled in dataflow graphs and how, using the same timing-analysis techniques, the timing behavior of the mapped application can then be verified. These ingredients constitute a model-based design-flow that maps a timing-constrained application, expressed as a dataflow graph, onto an MPSoC. The participants will experience such a mapping flow through a hands-on session within the tutorial. In this hands-on session, the participants use a state-of-the-art dataflow analysis and mapping tool to experiment with all material taught in the tutorial. The tutorial concludes with a demonstration that shows a complete design flow, mapping the software-defined radio application introduced at the beginning of the tutorial onto the presented CoMPSoC platform.

The tutorial consists of the following sessions:

  • (15 min.) Introduction to MPSoC design.
  • (30 min.) Modeling software defined radio (SDR) applications with dataflow.
  • (15 min.) Demonstration of the CompSOC architecture and SDF3 design flow.
  • (30 min.) Precision-Timed (PRET) Machines.
  • (30 min.) Predictability in the CompSOC platform.
  • (30 min.) Automatic application mapping to predictable MPSoCs.



Dr. Benny Akesson earned a M.Sc. degree in Computer Science and Engineering at Lund Institute of Technology, Sweden in 2005. In 2010, he received his Ph.D. degree in Electrical Engineering at Eindhoven University of Technology, the Netherlands, on the topic of "Predictable and Composable SoC Memory Controllers". This research was conducted in collaboration with NXP Semiconductors. Prior to joining the CISTER research unit in Porto, Portugal, Dr. Akesson worked as Postdoctoral Researcher and Assistant Professor at the Eindhoven University of Technology, where he is led the memory research team in the Electronic Systems group at the faculty of Electrical Engineering. His primary research interests include memory controller architectures, real-time resource scheduling, performance modeling, and virtualization.

Dr.ir. Sander Stuijk received his M.Sc. degree (with honors) in Electrical Engineering in 2002 and his Ph.D. degree in 2007 from the Eindhoven University of Technology. He is currently an assistant professor in the Department of Electrical Engineering at the Eindhoven University of Technology. Sander Stuijk has been working as a visiting researcher at the Technical University of Dortmund in Germany (2009). His research interests include modeling methods and mapping techniques for the design, specification, analysis and synthesis of predictable hardware/software systems.

Prof.dr. Kees Goossens received his PhD from the University of Edinburgh in 1993, on the formal verification of hardware, in particular by using semi-automated proof systems in conjunction with formal semantics of hardware description languages. After several post-doctoral positions he joined Philips Research in the Netherlands in 1995. He led the team that defined te Aethereal network on chip for consumer electronics, where real-time performance and low cost are major constraints. His DATE'03 paper was selected as one of the 30 most influential papers of 10 years of the DATE conference. He was also part-time full professor at the Delft university of technology from 2007 to 2010, and is currently full professor at the Eindhoven university of technology, where his research focusses on composable (virtualised), predictable (real-time), low-power embedded systems.

Dr. Orlando Moreira is a senior scientist at ST-Ericsson. He graduated in Electronics Engineering from the University of Aveiro. In 2012 he received his Ph.D. degree in Electrical Engineering from the Eindhoven University of Technology. Before joining ST- Ericsson, he worked for Philips Research and NXP Semiconductors. In 2007-2008, he led a joint Nokia, NXP and ST-Ericsson team in developing a hard-real-time software architecture for radios. He published work on reconfigurable computing, real-time multiprocessor scheduling, and dataflow analysis.

Dr. Jan Reineke studied Computer Science and Economics at the University of Oldenburg and Saarland University, obtaining BSc and MSc degrees in 2003 and 2005. In 2008, he received a Ph.D. form Saarland University with a thesis on the predictability of caches. His thesis was nominated for the ACM Doctoral Dissertation Award. From 2009 until the end of 2011, he was a postdoctoral scholar at the University of California, Berkeley, where he was working on timing-predictable architectures within the PRET project. In 2012, he became an assistant professor at Saarland University. In the same year, he was named an Intel Early Career Faculty Honor Program Awardee.