Efficient Retiming of Multi-rate DSP Algorithms
Multi-rate digital signal processing (DSP) algorithms are often modeled with synchronous dataflow graphs (SDFGs). A lower iteration period implies a faster execution of a DSP algorithm. Retiming is a simple but efficient graph transformation technique for performance optimization, which can decrease the iteration period without affecting functionality. In this paper, we deal with two problems: feasible retiming - retiming an SDFG to meet a given iteration period constraint; and optimal retiming - retiming an SDFG to achieve the smallest iteration period. We present a novel algorithm for feasible retiming and based on that one, a new algorithm for optimal retiming, and prove their correctness. Both methods work directly on SDFGs, without explicitly converting them to their equivalent homogeneous SDFGs (HSDFGs). Experimental results show that our methods give a significant improvement compared to the earlier methods.