Kees Goossens's Publications Page

Investigating NoCs In addition to the SPIRIT announcement, Philips Research Laboratories also presented the results of an investigation into the utility of using network-on-chip (NoC) technology to interconnect multiple ICs. NoC technology is viewed as a replacement to the on-chip bus, and offers advantages such as the ability to interconnect multiple IP cores, and increased data freedom in handling data between IP cores. Compared to a bus, however, it also suffers penalties in terms of chip area and dissipation. Philips Research Labs redesigned an existing bus-type application-specific IC (ASIC) for TVs to use NoC technology, and evaluated the resulting disadvantages. The change from bus to NoC increased chip area by 4.4%, and the 300MHz operating frequency of the NoC region increased dissipation by 10.8%. When the network configuration was changed from 2x2 to 1x3, however, the operating frequency of the NoC region dropped to 160MHz, with an increase in dissipation of only 5.4%. The 1x3 configuration does reduce the degree of network freedom, however. According to Kees Goossens of Philips Research Labs, the investigation indicated that the penalty is sufficiently low. As a result, designer interest in NoCs is rising, and he commented that the development of the first SoCs using NoC technology would be started in 2007.

In developing its Aethereal Network-on-Silicon (NoS), Philips decided to use a combination of circuit and packing switching, a la asynchronous transfer mode, to enable communications between IP blocks. Philips managers described NoS as "a hardware architecture with a programming model based on the OSI reference model, which allows the structuring of communication complexity from the physical implementation up to the application in a number of layers." In this way a communications-centric architecture in an SoC can be used to serve numerous specific applications, possibly leading one day to an entire application-specific SoC industry.